This invention relates generally to integrated circuit structures and methods for forming such, and more specifically to such structures and methods related to integrated circuit capacitor structures such as those found in dynamic random access memories.
Capacitor structures perform useful functions in a wide variety of integrated circuits. For example, dynamic random access memories (DRAMs) are common integrated circuits, used for storing digital data in computer applications, that make extensive use of integrated capacitors. The core of these circuits consists of rows and columns of DRAM xe2x80x9ccellsxe2x80x9d, each cell capable of storing one bit of information. Each DRAM cell contains a storage capacitor and an access transistor. The storage capacitor may be set to either a charged or a discharged state, with the charge storage state representing a xe2x80x9cstoredxe2x80x9d bit of information. This charge storage state may later be read to determine the value set in the DRAM cell.
The amount of charge stored in a charged DRAM cell is related to the specific capacitor design. The minimum charge storage requirement for the DRAM cell storage capacitor is generally driven by the DRAM read circuit""s ability to reliably discriminate between the capacitor""s charged and uncharged states. As charge storage is directly related to the area of the storage capacitor, a designer wishing to shrink the size of a DRAM cell must therefore compensate for the reduced capacitor area in some manner, or the reduction in charge storage capacity will cause the circuit to operate unreliably. Many different means, some of them very elaborate, have been suggested for maintaining the required charged storage with a smaller capacitor circuit area. These means include trenched and stacked capacitors (which use at least some vertically-integrated charge storage structure to compensate for the decrease in lateral charge storage capability), and capacitors with high permittivity dielectrics.
High permittivity (high-k) dielectrics can compensate for capacitor area reduction, as capacitance is directly proportional to dielectric constant (the dielectric constant of a material is the ratio of the permittivity of the material to the permittivity of free space). Thus, all else being equal, a device with a dielectric constant of 40 can store roughly 10 times the charge of a similar-sized device employing a conventional silicon dioxide dielectric. Unfortunately, substitution of high-k materials for silicon dioxide opens up a host of material compatibility and processing issues. Many of these issues are related to the requirement that most high-k materials must be formed and/or annealed in high-temperature, highly-oxidizing conditions. As such, these materials generally cannot be formed directly over a silicon or other oxidizable electrode without also causing a portion of the electrode to oxidize, thus greatly degrading the capacitive properties of the device.
Many alternative electrode materials have been proposed to avoid the electrode oxidation problem found with high-k material deposition. These range from noble metals that resist oxidation, such as platinum, to conductive oxides that are pre-oxidized, such as ruthenium dioxide, to conductive nitrides that also resist oxidation, such as titanium nitride. Many proposed electrode structures utilize these materials in electrodes comprising multiple layers of dissimilar materials. In general then, alternative electrode materials and processes add complexity and expense to the fabrication process.
As a simpler and less expensive alternative, silicon electrodes (highly doped Si) have been used, e.g., with tantalum pentoxide dielectrics, by forming a thermal silicon nitride barrier layer on the surface of the silicon electrode prior to deposition of tantalum pentoxide. Although this approach is relatively straightforward, it is not without its own problems. Thermal nitridation generally requires temperatures in excess of 900xc2x0 C., an unattractive requirement at this stage of the fabrication process when other temperature-sensitive circuit devices have already been formed. Also, the nitride must be thick enough to inhibit oxidation of the silicon (generally on the order of 30 xc3x85 or more). As silicon nitride has a dielectric constant of only 7, the formation of a 30 xc3x85 silicon nitride barrier may severely limit achievable overall dielectric constant even when combined with a high-k dielectric such as tantalum pentoxide.
The present invention comprises an integrated circuit having a capacitor structure with a high charge storage density, and a method for making the same. The present invention makes possible the economical construction of high-k capacitors with silicon electrodes at relatively low temperature, apparently with minimal formation of interfacial oxide layers that degrade performance. Devices fabricated by the method of the invention have been measured with charge storage capacity comparable to a theoretical device having a silicon dioxide layer only a few monolayers thick.
The present invention avoids formation of silicon dioxide on a silicon electrode during dielectric deposition by initially forming an ultrathin passivation layer on the silicon electrode. In general, this passivation layer is formed by briefly exposing a clean silicon electrode to NO, preferably at 700xc2x0 C. to 800xc2x0 C. It is now believed that the resulting silicon oxynitride passivation layer is strongly resistant to further oxidation, even when formed at thicknesses less than 1 nm. Although the passivation layer itself is believed to have a relatively low dielectric constant, because the passivation layer may be made extremely thin it has a relatively small effect on the overall capacitor dielectric constant.
The present invention is believed to have other benefits as well. Because of the relatively low temperatures and short NO exposure times preferred in the invention, other devices on the circuit do not have to withstand a long high-temperature anneal in order to form the passivation layer. Also, the method of passivation layer formation is straightforward and should be applicable to any electrode shape. And, the NO exposure step is believed to result in relatively high nitrogen concentrations in the oxynitride layer, particularly at subnanometer dimensions.
In one aspect of the invention, a method of fabricating an integrated circuit is disclosed that comprises providing a substrate having a silicon electrode with either a bare Si or a hydrogen-terminated Si surface thereon, this surface being substantially unoxidized. This method further comprises forming a silicon oxynitride layer on this surface with an average thickness of less than 1 nm (and more preferably less than 0.5 nm), by exposure to NO. This method further comprises forming an alternative dielectric material layer on the oxynitride layer. The silicon electrode may be either single-crystal silicon or polycrystalline silicon (polysilicon).
Alternative dielectric materials are defined herein to comprise: metal oxides other than silicon dioxide, complex metal oxides, and metal silicates. Most preferably, the alternative dielectric material has: 1) a dielectric constant on the order of 10 or greater, such that the alternative dielectric layer may be formed significantly thicker than a layer of silicon dioxide delivering similar capacitive performance; and 2) a heat of formation that is more negative than the heat of formation of silicon dioxide, which is believed to aid in the formation of a stable dielectric via the method of the invention. Preferable metal oxides include those with metals selected from Groups IIA-VIA (e.g. BaO, CeO2, HfO2, La2O3, Nb2O5, Ta2O5, TiO2, V2O5, WO3, and ZrO2). Preferable complex metal oxides include those comprising metals selected from Groups IIA-VIA (e.g. BaTiO3, BaWO4, (Ba,Sr)TiO3, SrTiO3, and SrWO4). Preferable metal silicates include those comprising metals selected from Groups IIA-VIA (e.g. (Al2O3,SiO2), CeSiO4, HfSiO4, LaSiO4, TaSiO4, and ZrSiO4). Although such silicates need not be stoichiometric, they are selected to contain both silicon dioxide and metal oxide at significantly greater than incidental impurity levels.
Preferred processing conditions for the step of NO exposure are believed to be optimized by temperatures of between 700xc2x0 C. and 800xc2x0 C., with 700xc2x0 C. being more preferable. Exposure times are preferably within the range of 1 to 100 seconds, with shorter exposure times preferred. NO partial pressure during oxynitride film growth is preferably in the range of 1 to 10 Torr; this may consist of pure NO at this pressure, or NO in an inert carrier gas such as argon.
In another aspect of the invention, an integrated circuit having a capacitor fabricated thereon is disclosed, wherein the capacitor comprises a silicon electrode with a dielectric layer of an alternative dielectric material overlying it. A silicon oxynitride layer having a thickness less than 1 nm and formed by exposure of the silicon electrode to NO is interposed between the electrode and the dielectric layer. A conductive layer may then be formed over the dielectric layer.